There exists a persistent incentive in the semiconductor industry to fabricate integrated circuit (IC) devices of increasing complexity. As is well known, increased complexity of an IC product results in fabrication costs that increase commensurately. In order to provide IC devices having enhanced functional capability, while appropriately managing the cost associated with device fabrication, the number of devices included on each semiconductor wafer must be continually increased. In recent years, developments in IC fabrication technology have enabled the ability to define circuit components having feature sizes in the submicron range. For example, new lithographic techniques have been developed using x-ray and deep UV energy sources. In addition, film deposition technology now exists that forms thin films having a precisely determined metallurgical composition and thickness. Furthermore, thin-film etching techniques have been developed that are capable of selectively etching a specified metallurgical composition, while preserving in tact other metallurgical compositions present on. the semiconductor substrate.
However, notwithstanding the marked advances in semiconductor fabrication technology, realization of the necessary device density and cost control in the manufacture of contemporary IC products require further processing innovations. As device dimensions, such as the gate length of metal oxide semiconductor (MOS) transistors, continue to be compacted, additional physical process limitations come into play.
A significant impediment to further size reduction of MOS transistors derives directly from the physical limitation of lithographic technology. Photolithographic techniques utilize an optically sensitive resist material that is formed on a semiconductor substrate. A photolithographic mask having a predetermined pattern is aligned to the semiconductor wafer, and light is passed through the mask. After exposing the resist, the resist is developed and selectively etched away to form a pattern on the wafer. Photoresist exposure steps typically require precision alignment of the mask with the wafer. The minimum feature size that can be photolithographically defined is constrained not only by limitations that inhere in alignment precision, but also by optical diffraction. To reduce the effects of diffraction in lithographic operations, state-of-the-art processes have resorted to the use of deep UV lithographic techniques, recognizing that diffraction anomalies vary inversely with the frequency of the optical energy source. However, even deep UV lithography is not able to reliably define feature sizes below approximately 100 nanometers (nm).
Consequently, the fabrication of MOS transistors with gate structures on the order of 100 nm requires processing technology beyond existing lithographic and resist formulation technologies. In many ways, the smallest feature size to which an MOS gate electrode may be fabricated dictates the scaling of all other device components in an IC device. The feature size of a MOS gate electrode must be continuously reduced in order to improve the performance and operational capabilities. Accordingly, a sophisticated fabrication process is necessary to reliably manufacture device components, such as MOS transistors, having gate lengths on the order of 100 nm or less.
To further enhance the performance of lithographic technology, manufacturers have developed advanced resist materials and coatings, such as antireflective coatings (ARCs) and the like, that improve the ability of optical lithography to produce submicron features. Additionally, post-feature-definition techniques, such as photoresist trimming, are also used to reduce the feature dimensions below the prevailing photolithographic limit. Although advances in resist materials and processing methods have extended the limits of lithography, the precise formation of extremely small feature sizes remains beyond the grasp of present process technology.
An alternative approach to the formation of MOS transistor having narrow gate lengths that are not realizable with existing photolithographic techniques is disclosed in U.S. Pat. No. 6,060,377, Method for Fabricating a Polysilicon Structure With Reduced Length That Is Beyond Photolithography Limitations. The technique disclosed there is predicated on a silicidation anneal to achieve reduced gate length. A masking polysilicon structure is first formed on a hardmask layer and is then patterned by reactive ion etching (RIE). A metal layer of predetermined thickness is formed by chemical vapor deposition (CVD) over the top and contiguous to the sidewalls of the patterned masking polysilicon structure. An anneal is performed to form a metal silicide with the sidewalls of the masking polysilicon structure. The metal silicide is ultimately removed with a selective wet etch to reveal a masking polysilicon structure of reduced length. This masking polysilicon structure is then used as a mask for the formation of the gate structure of a MOS transistor.
Without unwarranted derogation of the effectiveness of the above process in the formation of MOS devices of reduced gate length, practitioners skilled in the art of semiconductor device fabrication nonetheless recognize that such a process is not particularly auspicious for its simplicity. To wit: a number of process steps, the salient one of which is a silicidation anneal, must be performed in order to acquire a polysilicon mask with the desired feature size. Additional processing subsequent to the silicidation anneal is required for the formation of the ultimate gate structure. Accordingly, a technique for achieving a reduced-gate-length MOS transistor with more favorable process efficiency and simplicity would constitute a welcome advance in the state of the art.
Skilled artisans appreciate that elements in Drawings are illustrated for simplicity and clarity and have not (unless so stated in the Description) necessarily been drawn to scale. For example, the dimensions of some elements in the Drawings may be exaggerated relative to other elements to promote and improve understanding of embodiments of the invention.